Technical Field
This disclosure relates to the field of integrated circuit (IC) chip architecture and layout, and more particularly to the efficient routing of interconnect lines and bus lines.
Description of the Related Art
FIG. 1 is a block diagram of one example of a multi-core computer architecture in which numerous buses carry data between partitioned sections of a conventional integrated circuit die 10. In particular, the integrated circuit die 10 is a system-on-chip (SOC) that contains microelectronic components having transistors and interconnect wiring formed in and on a semiconductor substrate. The microelectronic components generally include one or more microprocessors 14 and a number of support components 12 that support operations of the microprocessors 14. The microprocessors 14 can include, for example, central processing units (CPUs), graphics processors, digital signal processors (DSPs), microcontrollers, and the like. The support components 12 can include any of the many types of operating units on the integrated circuit die 10, including memory, which may be RAM, ROM, EPROM, flash, cache, and the like. The support components 12 may also include memory exchange interfaces, shift registers, accelerator logic blocks, peripheral circuits, arithmetic logic units (ALUs), display drivers, power supplies, voltage regulators, clock circuits, timers, and any number of memory arrays or logic units that are required for the integrated circuit die 10 to operate properly. An SOC integrated circuit die may be used to build, for example, multimedia content receivers such as cable or satellite TV set top boxes; cable and internet modems; wireless routers; laptop computers; tablet computers; smartphones, or other electronic hardware items.
With the proliferation of multi-core chip architectures, the need for many wiring layers to interconnect all the different support components 12 and the microprocessors 14 to each other has greatly proliferated. Accordingly, a large number of busesl, along with bus bridge circuits 18, are now used on the integrated circuit die 10 in order to properly connect all of the components to each other and ensure proper chip operation.
Interconnection lines, generally referred to as buses 1, provide connectivity between the various support components 12 and microprocessors 14. In addition, bus bridge circuits 18 link the buses to each other. Any component on the integrated circuit die 10 can be coupled to any other component for which it needs a connection for proper operation.
FIG. 2A illustrates an existing exemplary layout of the integrated circuit die 10, which is a system-on-chip (SOC) having a die size of about 100-120 mm2. In FIG. 2A, structures similar to those shown in FIG. 1 are labeled with the same reference numbers. FIG. 2A clearly shows the interconnects of the integrated circuit die 10, which has a multi-core microprocessor architecture generally of the type as shown in FIG. 1. Specifically, the layout shown in FIG. 2A indicates locations of a number of microprocessors 14, support components 12, including memory units, a number of ALUs, DSPs, bus bridge circuits, and other support components 12, relative to the buses 1. The circuit designs for the various components are grouped together and organized into separate units, or design partitions 15, and arranged on the integrated circuit die 10 at convenient locations. The design partitions 15 may or may not be aligned with physical boundaries of the various microelectronic components. Specifically, the chip design shown in FIG. 2A includes a number of support components 12 as well as microprocessors 14 that can be considered as a group within each design partition 15.
In FIG. 2A, a number of buses 1 connect the various components with each other using channels 17. As detailed in the enlarged view in FIG. 2B, the channels 17 are regions of open space on a chip, located between design partitions 15 (15e, 15g) that are set aside specifically to accommodate the buses 1 to route signals and data between different components. The channels 17 are selected areas outside of any partition 15 reserved for electrical interconnections in the buses 1 that provide main communication arteries for wires connecting the different components. According to existing architectures a number of channels 17 are provided that are routed through various portions of the integrated circuit die 10, which can be seen in FIG. 2A as electrical wires running along the surface of the chip to connect the various components.
Conventional chip designs typically require that all of the interconnection lines and buses 1 between major partitions 15 and components 12 run in the channels 17 so that noise is suppressed and proper maintenance of clock signals is provided. Specifically, a number of amplifiers, repeat stations, and clock buffer circuits are provided in the silicon substrate under the channels 17 in order to maintain and provide consistent clock signals to the different components at the proper strength as they travel to different components in the integrated circuit die 10.
On an SOC die of size 100-120 mm2, some of the channels 17 may be up to 100-150 μm wide to accommodate thousands of interconnecting wires, which would otherwise be usable chip real estate. The channels 17 may take up in the range of 5-8% of the surface area of the die, generally occupying, on average, approximately 6% of the chip area. In addition, the requirement to run interconnection lines and buses 1 within the channels 17 causes the lines to be significantly longer than would otherwise be needed if a direct connection were possible. This slows down chip operation, requires additional clock buffer circuits, and introduces delays. For example, clock delays and signal propagation delays may occur, which delays interfere with efficient chip operation and must be accommodated for by additional circuits.
The integrated circuit die 10 includes a ring of communication lines 9 around an edge of the die that are coupled to the transmission lines in the channels 17. Often signals from some of the internal partitions, like 15g, that need to communicate with the partition 15d will travel along the zig zag path of the channels 17 to the ring 9 to get to 15d. It is a long and convoluted path. These channels 17 do not pass over or through intervening partitions. For example, if partition 15f needs to talk to partition 15a, the channels do not pass through or over partitions 15d, 15b, or 15e, and instead travel around the edge of the die.
As can be seen in FIG. 2C, the ring 9 is a wide conduction line that is capable of transmitting large signals. The ring separates a pad region 8 from the partitions 15b, 15c, and 15d. The pad region 8 allows the die to be coupled to an external device, such as a printed circuit board or another die.